768 megabit synchronous dram dpsd96mx8wky5 description: the lp-stack? series is a family of interchangeable memory modules. the 768 megabit sdram is a member of this family which utilizes the new and innovative space saving tsop stacking technology. the modules are constructed with 32 me g x 8 sdrams. this 256 megabit based lp-stack? module, the dpsd96mx8wky5 has been designed to fit in the same footprint as the 32 me g x 8 sdram tsop monolithic and 256 megabit sdram based family of lp-stack? modules. this allows the memory board designer to upgrade the memory in their products without redesigning the memory board, thus saving time and money. features: ? configuration available: 96megx8(3 banks of 8 mx4x8 bits) ? clock frequency: 66 [1] ,83 [1] , 100, 125 [2] , 133 [2] mhz (max.) ? pc100 and pc133 compatible ? 3.3v supply ? lvttl compatible i/o ? four bank operation ? programmable burst type, burst length, and cas latency ? 8192 cycles / 64 ms ? auto and self refresh ? package: tsop leadless stack notes: [1] available in industrial temperature ranges only [2] available in commercial temperature range only. advanced information 1 30a226-30 rev. a pin-out diagram (top view) 33 a8 vcc 1 dq0 2 54 vss vccq 3 53 dq7 n.c. 4 52 vssq dq1 5 51 n.c. vssq 6 50 dq6 n.c. 7 49 vccq dq2 8 48 n.c. vccq 9 47 dq5 n.c. 10 46 vssq dq3 11 45 n.c. vssq 12 44 dq4 cs2 13 43 vccq vcc 14 42 n.c. cs1 15 41 vss we 16 40 n.c. cas 17 39 dqm ras 18 38 clk cs0 19 37 cke ba0 20 36 a12 ba1 21 35 a11 a10 22 34 a9 a0 23 32 a7 a1 24 31 a6 a2 25 30 a5 a3 26 29 a4 vcc 27 28 vss pin names a0 - a12 row address: a0 - a12 column address: a0 - a9, a11 ba0, ba1 bank select address dq0 - dq7 data in / data out cas column address strobes ras row address enables we data write enable dqm data input/output mask cke clock enable clk system clock cs 0-cs 2 chip selects v cc /v ss power supply/ground v ccq /v ssq data output power/ground n.c. no connect functional block diagram a0-a12 cas we 256 mbit sdram dq0-dq7 cs0 (4x8mx8bit) (4x8mx8bit) ras cke clk cs1 dqm ba0,ba1 cs2 (4x8mx8bit) this document contains information on a product presently under development at dense-pac microsystems, inc. dense-pac reserves the right to change products or specifications herein without prior notice.
dpsd96mx8wky5 dense-pac microsystems, inc. notes: [1] available in industrial temperature ranges only, see note 4. [3] contact your sales representative for supplier and manufacturer codes. [2] available in commercial temperature range only. [4] all industrial temperature range parts are subject to availability of screened components. advanced information part numbering description 2 30a226-30 rev. a mechanical drawing .020 [.51] .0315 [.80] .0305 [.775] top view side view bottom view end view pin 1 index .502.008 .150 max. .0335 [.85] .885.010 .407 [10.34] .397 [10.08] .527 [13.39] .517 [13.13] .0315 [.80] bsc .018 [.46] standard tsop pad layout is acceptable, however, when possible, the following pad layout is recommended for optimal manufacture and inspection. see application note 53a001-00 for further information. [12.75.20] [22.48.25] [3.81 max.] .819 [20.80] bsc .022 [.56] [11.76.20] .463.008 manufacturer code p1 dp xx xx - speed memory prefix pc100 sd 96m x 8 y5 package memory desig memory type memory module without support logic depth width desig wk stackable tsop synchronous dram 10ns (100mhz) 8ns (125mhz) 08 10 supplier -dp supplier code 256 megabit lvttl based 15 12 12ns (83mhz) 15ns (66mhz) cl x grade x cas latency 2 2 i industrial temperature commercial temperature blank [1] [1] [2] [3] [3] [2] [1] [1] [2] [2] 75 7.5ns (133mhz) [4] [4] 7321 lincoln way, garden grove, california 92841-1431 ? (714) 898-0007 ? (800) 642-4477 ? fax: (714) 897-1772 ? http://www.dense-pac.com
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